Assertion to test 3 signals where when A goes high it should for B or C to go high and checking should continue till a is high

SystemVerilog
2

In reply to bhajanpreetsinght:

If I have to really think about it because of the definition of the until, then I would rather find something that it clear and easier to read.
A |-> (B || C) throughout !A[->1]; // B||C ==1 when A==0

A |-> (B || C)[*1:$] ##1 !A; // B||C ==don’t care when A==0