In reply to guorke:
Your requirements are ambiguous and hard to follow.
I suggest that you clarifyyour requirements wth waveforms and a start of a SystemVerilog template. for example,
// this is not an assrsionb just my noted
// in struggling to understand the requirements
module top;
timeunit 1ns/100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
bit clka, clkb, x, z;
default clocking @(posedge clka);
endclocking
initial forever #10 clk=!clk;
initial begin
$timeformat(-9, 1, "ns", 8);
$display("%t", $realtime);
end
/* I need to implment a checker to check follow condition.
in clka toggle phase, set 'x' to high, then clkb should be toggled in 100T (unit is clka period) when 'x' is high
and 'z' should have raise a ack pulse (0-1-0) in clkb toggle phase. */
always @(@(clka) begin
realtime v;
bit ten_ps;
x<=1'b1;
v=$realtime;
@(clkb) $realtime -v==10ps;
assert(z==0);
ap: assert property(@(clkb) ack ##1 !ack);
#100000;
/* then set set 'x' to low
then clkb should stop toggling in 100T (unit is clka period) when 'x' is low
and 'z' should have raise a similar pulse (0-1-0) in clkb toggle phase. */
x<=1'b0;
v=$realtime;
// clkb should stop toggling in 100T (unit is clka period) when 'x' is low
fork
begin #10ps; ten_ps=1; end// need to define the units
@(clkb);
join_any
assert(ten_ps);
end