Assertion to find if there is any clock is active in a particular state in FSM

SystemVerilog
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2

In reply to sumanth291092:

  1. what is your definition of “clocks are active are not?”
    Toggling for ever until state changes?
  2. periods of the clock for each of the states?

I would approach this with separate concurrent tasks or fork-join task.

Have to think about it after I know more requirements.