In reply to sphen:
The reason your assertion always fails is that the Boolean expression (ck2==1) uses the sampled value of ck2, which is the value it has at the beginning of the of the time slot when @(posedge cl2) happens. So that will always be 0 (or X).
You need to be more specific about your condition, but I’ll assume you meant to say you want to check when signal is true n time in any overlapping 100 clock cycles. The most efficient way to do that would be to create 100 bit shift register with a 1 set each time your signal is true and assert that the count of ones is 5.
bit [1:100] count5;
always @(posedge ck) count5 = {count5,signal==1};
property
@(posedge ck2) enable |-> $countones(count5) == 5;
endproperty
You’ll need to enable the assertion after the first 100 clock cycles.
If the 100 clocks cycles is not overlapping, you can do something similar, but you’ll need to be more specific about how the period starts.