In reply to Anudeep J:
SVA relies on clocking events, typically a clock. Thus, the following is correct
assert1: assert property (@(posedge clk) $fell(a) |-> (b throughout c[->1]));
// Also, "stable" is defined as
// $stable returns true if the sampled value of the expression did not change between the
// sampled value at the previous cycle and the sampled value at the current cycle.
// Otherwise, it returns false. Thus,
assert_stable: assert property (@(posedge clk) ##1 $fell(a) |->
($stable(b) throughout c[->1]));
However, what you want is something that is asynchronous. For that, I suggest the use of tasks with fork/join_any. For example:
task automatic t1();
bit fail;
fork
begin : check_stable
@(b) fail=1;
end : check_stable
begin : at_end
@(posedge c);
end : at_end
join_any
assert(!fail) else $display("b is unstable %t", $realtime);
endtask
initial
forever @(negedge a) t1();
Read my paper: SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy