Assertion to check number of clock pulses

SystemVerilog
10

In reply to gv_bing:

My previous code snippet should be supported by most/all tools, see below:



  // 4.  cs_n goes high
  a_chk_sclk_16 : assert property
    ( @(posegde clk) $rose (cs_n) |-> sclk_count == 16 );

Are you saying the above isn’t supported?

Srini