Assertion to check for the pulses of the clock

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Thank you ben for you response.

let me re frame my question

  1. I have two phases shift phase and capture phase
  2. During Shift phase there is a clock running say frequency of 100 mhz.(In shift phase
    scan_en is 1 indicating that this clock is shift clock… lets name this “shift_clk”)
  3. Now, comes the capture phase by de-asserting the “scan_en” signal.
    a) In Capture phase, i.e scan_en is “0” I get functional clock… let us name it as
    “fun_clk”

My question is I wanted to check the frequency of “fun_clk” with the expected value.
We can parameterize the expected value.

For example the expected value is 500ns.
I want the “fun_clk” time period should equal to 500ns.
If this happens assertion pass else fail.

The reason I have mentioned 2 consequtive cycles in my previous post to get the time_period.

Thanks,
durga