Assertion to check for the pulses of the clock

SystemVerilog
2

In reply to durga:
If I understand your requirements:

  1. There is a running clock clk
  2. There is a scan_en control signal that gates the clk with an output called scan clock sc_clk.
  3. That sc_clk runs for N more clock cycles following the deassertion of the scan_en control signal
    With those requirements, you can write the following:

let N=2; 
ap_scan: assert property(@(posedge clk) disable iff (reset); // 50mhz
   $fell(scan_en) |=> sc_clk[*N] ##1 !sc_clk);
// signal sc_clk ==1 @(posedge clk) N cycles following the $fell(scan_en)
// Following those N cycles, signal sc_clk ==0

Ben Cohen
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