Assertion to check async signals toggling

SystemVerilog
7

In reply to Anudeep J:

Try


always @(a or b or c) begin
  a1: assert final (b === c) else $error("error");
  a2: assert final (a === c) else $error("error");
end

Can use assert #0 instead. Note:
Deferred assertions use #0 (for an Observed deferred assertion) or final (for a final deferred assertion in the Postponed region) after the verification directive.