Assertion to check async signals toggling

SystemVerilog
2

[code]In reply to Anudeep J:
Unchecked code:
You can do something like this


 
module m;
  bit a, b, x, a_ocr, b_ocr, x_ocr; // ocr for occurred
  always @(posedge b) begin b_ocr=1; #1 b_ocr=0; end 
  always @(posedge x) begin x_ocr=1; #1 x_ocr=0; end 
  always @(posedge a) begin a_ocr=1; #1 a_ocr=0; end 
  always_comb 
     assert #0 (a_ocr && b_ocr && !x_ocr); else $display("Error in abx");
endmodule