In reply to ben@SystemVerilog.us:
Thanks for the update Ben.
The signals are internal to design. There is no clock controlling it and all are asynchronous signals. Iam just taking design hierarchies to assign the values and using them.
I have 3 signals A,B,C. A is driven from Testbench, based on A, B changes and once the B changes, C also changes. I wanted to check these transitions. I hope if I write final, it should work as everything is stabilized at the end of time stamp. But it is not.