Assertion to check a signal is stable between two pulses

SystemVerilog
9

In reply to ben@SystemVerilog.us:

 // a variation in property declaration 
 bit v;
 @(posedge clk) $rose(A) |=>  ((1, v=sig) ##0 (v==sig)[*1:$] ##1 !sig) 
            intersect $rose(B)[->1];

One cycle after rose of A, a set of the sequence sig stable for 'n' clocks thereafter  followed by!sig occurs during a period oc cycles with!Bs followed by a B. Thus, 
 
A.   0 0 1 - //assertion successfully attempted 
SIG. - - - 1 1 1 0.// one possible sequence 
sig. - - - 0 0 0 0 // another possible sequence 
B.   - - - 0 0 0 1
// this set satisfies the assertion