Assertion to check a signal is stable between two pulses

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Hi Ben,

I have tried the code in my context as below:
property check_env;
@(posedge clk) ($rose(A) |=> (stable(sig))[1*:] ##1 !(B) intersect $rose(B)[->1];
endproperty
assert property(check_env)
$display(“Assertion pass”);
else
$display(“Assertion fail”);

But I am getting errors as below:
Expected specification terminator “;”
This error is seen after ($stable(sig))

Thanks,
Anjali