Assertion stable after two or more rising edge

UVM
, , ,
5

In reply to ben@SystemVerilog.us:

Thanks Ben for very good explanation with example.
But now i am getting confused with first _match operator what is the use of first match operator. If you can explain with example like above example it would be very helpful.

i am thinking use of first_match is if @cycle 2 thread 2 starts @cycle 5 antecedent of thread gets success so thread2 immediately check for stable valueof other signal . But still thread2 is not killed at @cycle7 again it antecedent gets success and again matches stable value of other signal .

So in order to avoid are using first_match operator ?

Please correct me if i am wrong.

Thanks