Assertion stable after two or more rising edge

UVM
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In reply to ben@SystemVerilog.us:

Hi Ben ,

i have question on above question itself . since if use first match operator what about when “A” goes zero third time how can we handle this.
i.e

First time when “A” goes zero and followed after some clock cycles again when “A” goes zero the antecedent gets triggered which then check stable value of Dist_value

ssert property (@(posedge clk) disable iff (!reset_n)
first_match(fell(a) ##[1:] $fell(a)) |-> $stable(dist_value));

Now what happens when “A” goes low for third time will it be considered as fresh new cycle of assertion check or will it be ignored since we are using first_match operator.

Thanks

Also sorry for my bad English