Assertion signal (a) and signal (b)

SystemVerilog
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8

In reply to ben@SystemVerilog.us:

Hi VE or Ben or anyone,
Do you know why I am getting this errors. How to fix the errors

"testbench.sv", 19: tb.ap_3athenb: started at 15ns failed at 15ns
	Offending 'b'
"testbench.sv", 19: tb.ap_3athenb: started at 25ns failed at 25ns
	Offending 'b'
"testbench.sv", 19: tb.ap_3athenb: started at 35ns failed at 35ns
	Offending 'b'

Thanks,
JeffD