Assertion signal (a) and signal (b)

SystemVerilog
,
5

In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for the code. I used the below stimulus to test the assertion.
I got the following error shown below

initial
  forever #5 clk = ~clk;

initial
begin
  @(posedge clk);              
  a=1; b=0;
  repeat(3) @(posedge clk);
  a=0; b=0;
  @(posedge clk);
  a=0; b=1;
  repeat(3) @(posedge clk);
  a=0; b=0;
end

"testbench.sv", 19: tb.ap_3athenb: started at 15ns failed at 15ns
	Offending 'b'
"testbench.sv", 19: tb.ap_3athenb: started at 25ns failed at 25ns
	Offending 'b'
"testbench.sv", 19: tb.ap_3athenb: started at 35ns failed at 35ns
	Offending 'b'

Thanks,
JeffD