Assertion signal (a) and signal (b)

Hi Ben,

This assertion says that for every attempt there should NOT be the case when
“a” is repeated 3 times and then followed
by another “a” in the same time frame when “b” is asserted.

Yes. Before the 4th “a” arrive, “b” should arrive.

Please help in resolving the assertion failed 3 times.
I put “a” 3 clk cycles and 1 clock gap, then “b” arrive
Assertion should not fail. Not sure why it failed 3 times

Thanks,
JeffD