Assertion Question

SystemVerilog
1

Assertion such that given 2 bit command can’t be equal to 2 more than 4 times within 60 clock cycles.

 sequence sixty_cycles;
         1'b1 ##60;
         
       endsequence
       
       sequence command;
         (cmd==2'b10)[=5];
         
       endsequence
    
       property command_check;
         always@(posedge clk) |-> not command within sixty_cycles;
         
       endproperty

Is my solution correct?

2

Were you able to compile this in EDAP? I am getting a compilation error for the manner in which you have specified the “sixty_cycles” sequence.

Error-[SE] Syntax error
Following verilog source has syntax error :
“assertion.sv”, 3: token is ‘;’
1’b1 ##60;

I am trying to figure out what is the correct way to specify the “no. of clock cycles”.