Assertion for walking 1's

SystemVerilog
3

Thanks Ben. I used function and tried it out.
Here is the revised logic:

module test;
  logic [3:0] data;
  bit clk;
  static logic[3:0] temp = 4'b1000;
  
function bit check1(logic [3:0] x);
  $display("the temp is: %b and x is: %b",temp,x); 
  if (temp == x) begin
    temp = {temp[0], temp[3:1]};
    return 1;
  end
  
  return 0;
  
endfunction
  
  property check1_data;
    @(posedge clk) '1 |-> check1(data);
  endproperty
  
  assert property(check1_data) begin
    $display("%b passed", data);
  end
    else begin
      $display("%b failed", data);
    end
  
  initial begin
    clk = 1'b0; 
    forever #5 clk = ~clk;
  end
    
  initial begin; 
    #4;
    data = 4'b1000;
    #10;
    data = 4'b0100;
    #10;
    data = 4'b0010;
    #10;
    data = 4'b0001;
    #4;
    $finish;
  end
endmodule

Assertion is passing with this. But wanted to check with you if this is good approach.
Thanks!