In reply to ben@SystemVerilog.us:
how about this one:
module tb;
bit [3:0] va = 4‘b0010;
property walk;
@(posedge clk);
bit[3:0] temp;
$countones(va) ##1 (1, temp = {va[0], va[3:1]}) ##0 (temp == va);
endproperty
In reply to ben@SystemVerilog.us:
how about this one:
module tb;
bit [3:0] va = 4‘b0010;
property walk;
@(posedge clk);
bit[3:0] temp;
$countones(va) ##1 (1, temp = {va[0], va[3:1]}) ##0 (temp == va);
endproperty