In reply to saritr:
You can use an immediate assertion. However, you need to identify your variables by their instances. Thus,
module m;
bit clk, tx_srstn;
tx_in_interface tx_in1(.*);
tx_out_interface tx_out1(.*);
// NOT sure if you ned to type cast the sqrt. If so, then
typedef logic [15:0] WORD;
// I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2),
always if(tx_in1.sin==4'H0001)
a_sin: assert(tx_out1.y == WORD'(tx_in1.xi/(2 ** 0.5)) );
// see 1800'2012 11.4.3 Arithmetic operators
//and every time cos equal to 1(dec) y will be xq/sqrt(2)
always if(tx_in1.cos==4'H0001)
a_cos: assert(tx_out1.y == WORD'(tx_in1.xq /(2 ** 0.5)) );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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