Assertion for parameterized module instances

SystemVerilog
,
5

In reply to megamind:

When using if, case, or for outside of a procedural block, they are considered generate statements. See section 27. Generate constructs in the IEEE 1800-2017 SystemVerilog LRM

Some example of localparams. Only WIDTH may be overridden

module exp #(int WIDTH=10, localparam real HALFWIDTH = WIDTH/2.0) (input bit a);
localparam real THIRDWIDTH =WIDTH/3.0;
parameter int DOUBLEWIDTH =WIDTH*2; // considered the same a localparam when parameters
                                    // are in the module header
  initial begin
    $display("WIDTH = %d",WIDTH);
  end
 //this is a generate-if
 if (WIDTH != 10) $fatal(0,"Width != 10");
endmodule : exp