Assertion for checking connectivity

SystemVerilog
,
2

Hi,
The below definition meets your requirement and it is reusable as well.


property ppt(bit x, bit y);
	@(x) y==x;
endproperty
	
AB: assert property (ppt(a,b));

CD: assert property (ppt(c,d));

Hope this helps.
Putta Satish