In reply to verif4life:
As an educator, I am reluctant to answer what you can easily write yourself and learn something in the process. Thus, I suggest that you look into 1800’2017: 16.13.1 Multiclocked sequences. Your requirements are a simple application of that along with the use of the implication operator (|->).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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