Assertion for 55mhz clock

SystemVerilog
1

write an assertion for 55mhz clock

this is my approach and this code is working fine for time, not working properly for realtime. Can some one find the issue?


`define PERIOD 10ns
 
module tb;
 
    realtime TON = `PERIOD * 9.09;
    realtime TOFF = `PERIOD * 9.09;
 
    bit clock;
 
    initial begin
        clock = 1;
    end
    always begin
        #9.09 clock = 0;
        #9.09 clock = 1;
    end 
 
    property check_ton(int ton_time);
        time current_time;
        (1, current_time = $realtime) |=> @(negedge clock) (ton_time == ($realtime-current_time));
    endproperty : check_ton
 
    property check_toff(int toff_time);
        time current_time;
        (1, current_time = $realtime) |=> @(posedge clock) (toff_time == ($realtime-current_time));
    endproperty : check_toff
 
    assert property ( @(posedge clock) check_ton(TON))
        $display($time," CHECK_TON : PASS");
    else $warning($time," CHECK_TON : FAIL");
 
    assert property ( @(negedge clock) check_toff(TOFF))
        $display($time," CHECK_TOFF : PASS\n");
    else $warning($time," CHECK_TOFF : FAIL\n");
 initial begin
   $dumpfile("dump.vcd");
   $dumpvars;
 end
    initial begin
        #50 $finish;
    end
endmodule
2

What is your timescale and precision?

3

1ns/1ns

4

This code fails for me regardless of using time or realtime.

You have several problems.

The PERIOD should be 1ns, or the other delays should be adjusted accordingly.

With a time precision of 1 ns, delays like #9.09 truncates to #9. Even if you change the precision to 1ps, $time returns an integer that is rounded to the nearest nanosecond.

current_time is still declared with a type time.

Avoid using the equality operator == with real numbers. Instead, refer to the article “Why 0.1 Does Not Exist In Floating-Point” for more information. I would convert real numbers to integers in picoseconds and then perform the comparison.