In reply to ben@SystemVerilog.us:
Ben,
I understands your answer but why (b === 1’bx) is not working? As you mentioned this is not suggested way but is it wrong way.
Thanks
In reply to ben@SystemVerilog.us:
Ben,
I understands your answer but why (b === 1’bx) is not working? As you mentioned this is not suggested way but is it wrong way.
Thanks