Assertion failing to check all cases

SystemVerilog
6

Thank you for the help, but I still don’t think I understand. In the following example, why does mypropGOOD work (finishes at 1us, 2us, 3us, 4us) but mypropBAD does not (finishes ONLY at 1us)?:


module top;
  logic [2:0] state = 3'b001;
  logic b = 0;
 
  initial 
    begin
      #1us state = 3'b010;
      #1us state = 3'b011;
      #1us state = 3'b100;
      #1us state = 3'b101;
      #1us $finish;
    end
 
  // doesn't work (I think)
  
  property mypropBAD;
    @(state[2], state[1], state[0]) (state!=3'b000) |-> (b==1'b0);			
  endproperty
 
  pbad: assert property (mypropBAD) $display("mypropBAD passed at %t",$realtime);
  else $display("mypropBAD failed at %t",$realtime);

  // works
    
  property mypropGOOD;
    @(state[2], state[1], state[0]) (state!=3'b000) |-> (b==1'b0, $system("") );			
  endproperty
 
  pgood: assert property (mypropGOOD) $display("mypropGOOD passed at %t",$realtime);
  else $display("mypropGOOD failed at %t",$realtime);
    
endmodule

Simulator Output for above:

    
    mypropGOOD passed at                 1000
    mypropBAD passed at                 1000  
    mypropGOOD passed at                 2000   [why didn't mypropBAD finish here too?]
    mypropGOOD passed at                 3000   [why didn't mypropBAD finish here too?]
    mypropGOOD passed at                 4000   [why didn't mypropBAD finish here too?]

Why do mypropBAD and mypropGOOD work differently when the only difference is a $system(“”) call which does nothing?

@(state[2], state[1], state[0]) (state!=3’b000) |-> (b==1’b0, $system(“”) ); // difference in bold