Assertion Failing Not sure why?

SystemVerilog
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6

In reply to ben@SystemVerilog.us:

Hi Ben,

  1. So LINE_COUNT is a 32 bit variable but I figured out that I don’t have to consider all of that.
  2. For LINE_COUNT[0] = 1 the value of Line count is 1. when LINE_COUNT[1] = 1 the value is 2.
  3. In between these 2 events (line count getting 1 → 2) there are many instances when AWREADY and AWVALID become high.
  4. When LINE COUNT is 1 and at the first occurrence of AWREADY and AWVALID both getting high, there will be some address value in the AWADDR bus. I have to poll/read that value and store.
  5. After some clock cycles, when LINE COUNT is 2 and at the first occurrence of AWREADY and AWVALID both getting high, there SHOULD be some different address value in the AWADDR bus, as per the specs. I have to poll/read that value and store in a different variable. This is what I have to check. The difference in the value between two stored addresses happens due to a user PROGRAMMED value in a register in the DUT.
  6. The DUT works on random clock frequency so it is difficult to tell exact numbers of clock cycles between LINE COUNT 1 → 2.

I hope I am more clear with the requirement.