In reply to ben@SystemVerilog.us:
Can never fail because if “b” is false, other threads of the consequent will be tested.
An assertion of the form
in reply to above answer:when a is true ,it will keep checking for b==1’b1 from next edge to till the end of simulation ,if b never becomes 1 assertion will fail(is this correct or wrong).
my problem is :when a is one, after few clock cycles delay(take it as ##8) b is also becoming one ,in this scenario also assertion is not passing, it should pass in this scenario.