Assertion does not fail!

SystemVerilog
,
2

In reply to a72:

I think you want

property p1;
    @(posedge clk)
    tagError && $rose(tErrorBit) |->  $rose(mCheck);
endproperty

Looking at this some more, you might want

property p1;
    @(posedge clk)
    tagError && ($rose(tErrorBit) | $rose(mCheck)) |->  $rose(mCheck) && $rose(mCheck);
endproperty