In reply to Timus:
Following conditions are met in this assertion,
When rst is deasserted (when FSM comes out of reset) and st == a, then it should remain in this state for minimum 5 cycles.
You can remove $fell(rst), if for anytime st == a then it should be in this state for minimum 5 cycles.
property cnt_p;
@(posedge clk) disable iff (rst)
$fell(rst) && (st == a) |=> $stable(st)[*4];
endproperty