Assertion Count

SystemVerilog
, ,
4

In reply to Timus:

Only local variables are allowed to be modified inside property, so you need to call some method from property to increment the counter. you can try something like this -


module top();

bit clk;
int count;

always #1 clk = !clk;

initial begin
  repeat(10) @(posedge clk);
  $finish;
end

property cnt_p();
        //@(posedge clk) (1) |-> (1,count=count+1);
        @(posedge clk) (1) |-> (1,t_inc_counter());
endproperty

count_ap: assert property(cnt_p());

task automatic t_inc_counter();
 count++;
endtask

endmodule