Assertion check for a signal which depends on 2 other signals

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for reply. It helped me a lot and i changed my assertion little to have proper checks as per my requirement.

I have a question that how can we pass a variable inside a property.
ex: if i need to wait 4 repetitions of signal a i use a[->4], in the same way if i want to use a variable in place value 4 like a[->x]. so here x is configurable. I want to use variable because it is configurable from 0 to 7.

Same thing i need to apply for the this property which you replied.

Please help me how can i do that?

Thanks,
Murali