In reply to ben@SystemVerilog.us:
Ben,
Of-course we love confrontations :-) But in this case I don’t see one. We are augmenting each other well. My code was to show the core of “checking”, all around needed for a formal tool needs to be done by user. FYI - some FV tools don’t treat assume as is by default and require config/TCL files to do so. Unless the OP says which tool/version he uses it will be difficult to freeze. But I hope he can take it from here.
With due regards,
Srini