In reply to ben@SystemVerilog.us:
Change
fifo_empty_a : assert property (@(posedge clk) disable iff (!rst_n)
!started ##0 (enb== 0, set_started(1)) |-> x_out==0);
To
fifo_empty_a : assert property (@(posedge clk) disable iff (!rst_n)
!started |-> x_out==0);
I had the function call for simulation. Not needed