Assert Property vs Cover Property

SystemVerilog
3

In reply to cool_cake20:

If so, why not always to use both of them? ‘assert’ will check a failure of the rule/property, ‘cover’ will check whether the rule/property was ever fulfilled…

For example:

 sequence s;
    @(posedge clk) a ##1 b;
  endsequence

  property p;
    a |-> s;
  endproperty

  assert property (p);
  cover property (p);