Assert property (@(posedge clk) (signal==0) |-> 2==3) returns "true"

SystemVerilog
,
3

Ben, could you explain in short why the below both expressions are evaluated as TRUE? What’s wrong?

assert property (@(posedge clk) (sig==1));
assert property (@(posedge clk) (sig==1) |-> 2==3);

I understand that you are promoting your book, but anyway…

P.S. I already have your book, but still don’t understand how this may happen… If the first expression is evaluated to TRUE, how the second one might be also TRUE???