In reply to Tudor Timi:
Because the language is designed to execute what you wrote, not what you wanted to write. SystemVerilog may not be the strongest typed language out there, but it does have fixed set of rules for determining bit lengths. If we start changing the rules for every situation we think the user wants, the LRM would become exponentially bigger than it already is. And just look how sbellock misinterpreted what they thought bmorris wanted.