Array reduction sum method with clause overflow protection

SystemVerilog
6

In reply to dave_59:

Thank you, Dave.
So, are you saying the default size of “10” in this constraint

(array.sum() with (48'(item)) == **10**;)

is 32 bits.
Hence the sum of 'h13 + (9 * 'hFFFF_FFFF)when exceeds 32 bits, it gets truncated to lower 32 bits that is == 10.

Code I ran:


class arr;
  rand int unsigned array[];
 
  constraint array_sum_c {
              array.size() == 2;
	      //array.sum() == 10; //with (48'(item)) == 10;
	      array.sum() with (4'(item)) == 'd10;
              }
endclass
 
module top;
  arr a;
  initial begin
	a = new();
	repeat(5) begin 
		void'(a.randomize());
		$display("%p", a.array);
		$display("sum = %0x", a.array.sum());
	end
  end
endmodule

I have rerun the original program in this thread constraining the array size to 2 and qualifying size of array item with 'd4. I get the following result:
'{556349363, 4253430535}
sum = 1eaf6aba
'{540725342, 2194362796}
sum = a306220a
'{936386833, 1457103433}
sum = 8ea9c35a
'{1157917028, 2189035990}
sum = c77e733a
'{1767679275, 2519606847}
sum = ff8acb6a

In this case, the lower 32 bits of sum is not 10.
How does the constraint solver assumes the constraint “==10” is met?