In reply to Raja VA:
Arrays of instances are not true arrays of identically typed data elements and have to be handled specially at elaboration, not dynamically during simulation. Features like parameter overrides and port coercion can potentially make each instance element have different types and structures. The index into a true array is simply a computed offset into memory selecting a uniformly shaped element.
SystemVerilog treats the index of an array of instances (or generate for-loop of instances as part of the scope name. So mst_if[0], mst_if[i], … might as well be mst_if_zero, mst_if_one,…