Arranging/Including classes in multiple files

In reply to dave_59:

In reply to totochan1985:
It would really help to show some code and especially the error message you are getting.
Also you import a package, ni include it. See SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

Above is the code. It works on the playground but when I try to compile it on Questasim, it throws errors such as “transaction definition not found”.