In reply to MICRO_91:
realtime is equivalent to real.
time is equivalent to logic [63:0].
In earlier versions of Verilog, integers, reals, and time types had implementation dependant number of bit of resolution. Now all built-in types are fixed.
rtdelay stores the real value 800.559. Time scales and precision only apply to expressions using in delay constructs. Not until the appearance of #rtdelay do the scaling and precision apply.