APB READ_TRANSFER

UVM
10

In reply to vlsique:

before change the code the uvm sequence like below ,i randomize penable,psel,pwrite directly here…
typedef enum {READ, WRITE} kind_e;
rand bit [31:0] addr; //Address
rand logic [31:0] data; //Data - For write or read response
rand logic penable;
rand logic psel;
rand logic pwrite;
rand kind_e apb_cmd;
so the sequence_item was :-
assert(rw_trans.randomize() with { addr==32’h6523_1221;data == 32’h1021_2321;apb_cmd == 1’b0;penable==1’b1;psel==1’b1;pwrite==1’b1});
finish_item(rw_trans);
but now,

i’m directly hard coded the psel,pwrite,penable values in uvm_driver only

case (tr.apb_cmd)
1’b1: drive_read(tr.addr, tr.data);
1’b0: drive_write(tr.addr, tr.data);
endcase
//Handshake DONE back to sequencer
seq_item_port.item_done();
end
endtask: run_phase
virtual protected task drive_write(input bit [31:0] addr,
input bit [31:0] data);

  this.vif.master_cb.paddr   <= addr;             
 @(this.vif.master_cb);
  this.vif.master_cb.pwdata  <= data;
  
 this.vif.master_cb.psel    <= '1;
 this.vif.master_cb.penable <= '0;
 this.vif.master_cb.pwrite  <= '1;

////////
k…