@All,
Follow-Up Question:
a. Say as you suggested, have a reference model which does processing and predicts the desired behavior of the DUT.
SCENARIO:
- Say after process X, the DUT has updated the DUT status register(internal operation).
- Seeing the register changes, the testbench does a backdoor process and updates the register model to keep track of the DUT internal updates. So this internally changes the mirror value and the desired values of the register model.
- At the same time, the reference model tries to update the desired values of the register model. Can both happen at the same time and cause problem ? Or because of simulation time semantics, once after the DUT updates ~ then the reference model updates the register model ?
b. So is it better to have separate register model for the reference model, so that the desired/correct status flag etc. registers values can be maintained and later compared with the RTL ~ register model ?
c. Or is it better, that the reference model update the desired value of the register model and in-turn can be compared with the mirror-value which the DUT has updated ?
Kindly comment on the same and suggest some good coding practice for such scenarios !!
Thanks in Advance !
UVMmmmmmmmm :-)