In reply to perchrc:
I see the benefits of the include*. I just don't believe that it is a good idea to hard-line SVA into the RTL; it should be in a separate file. Note that unlike the *include, the binding of the same checker (or module) to different entities (module, or interface [if checker] ) allows the use of different actual arguments.
One could argue that this is not really serious since the bound element ties to entities that have port-list, so the names of the variables and parameters used in the SVA file are the same as the formal argument of the RTL, thus there is no need for all that argument association when the `include is used. Anyway, just passing on something to consider.
On Inability to add assertions in SV interfaces. (?), SystemVerilog provides the checker construct that can be bound to an interface.
Ben Cohen SystemVerilog.us