Hi, I have doubt on AND operation in assertions. Can somebody explain example no 16.6,section 16.9.6,page no :-404 in LRM IEEE Std 1800-2017. In that example how there is a match on 13th tick for composite sequence?. Here is the example :- (te1 ##[1:5] te2) and (te3 ##2 te4 ##2 te5) where te1,te2…

In reply to sasi_8985 : (te1 ##[1:5] te2) and (te3 ##2 te4 ##2 te5) // same as ((te1 ##1 t2) or (te1 ##2 t2) or (te1 ##3 t2) or (te1 ##4 t2) or (te1 ##5 t2)) and te3 ##2 te4 ##2 te5); // same as ((te1 ##1 t2) and (te3 ##2 te4 ##2 te5)) or // in evaluation at t9 ((te1 ##2 t2) and (te3 ##2 te4 ##…

AND operation on sequences in assertions

SystemVerilog

sasi_8985 March 1, 2021, 6:17am 5

In reply to ben@SystemVerilog.us:

Thank you Ben. Got it

Assertion for conditional sgnal monitoring