An interesting polymorphism behavior/mis-behavior?

SystemVerilog
,
1

I’m trying to play with polymorphism and notice something interesting. Not sure if it is related to tool or it is the correct behavior defined in LRM. In following code, I define 3 classes:

  1. A is the base, B extended from A, C extended from B. They all contain a function called showMsg;
  2. In A, showMsg is non-virtual, it has no argument;
  3. In B, showMsg is virtual, it has one argument, but no default;
  4. In C, showMsg is virtual, it has one argument, default to 0;

I expect when I assign c to b, then do “b.showMsg()”, it should call showMsg from C. In other words, I don’t need to provide an argument as the default is 0. However, VCS gives me a compile error. I have to provide an argument to make it work, and in this case the implementation is indeed from C. So it seems polymorphism is for the implementation part, not the argument default?

Another thinking is that maybe VCS should give a compile error when I try to add a default to C::showMsg? Should the prototype (including argument default) be exactly the same for polymorphism?

 module test;
   class A;
      function void showMsg();
         $display("This is A");
      endfunction
   endclass
   class B extends A;
      virtual function void showMsg(int val);
         $display("This is B, val = %0d", val);
      endfunction
   endclass
   class C extends B;
      function void showMsg(int val = 0);
         $display("This is C, val=%0d", val+1);
      endfunction
   endclass
   initial begin
      A a;
      B b;
      C c;
      b = new();
      a = b;
      a.showMsg();
      c = new();
      b = c;
      b.showMsg(); // I get a compile error!
   end
endmodule