In reply to ben@SystemVerilog.us:
On the overlapping/non-overlapping implication operator, yes, I now understand that the increment/decrement will start only on the edge that samples the ld to be low (which is the next edge after ld is high in our case).
As for the reset value check, I see that the assertion passes at time t=1ns. However, I am unable to understand:
-
Can we add such an assertion outside of an procedural block? (After all, we want to check that the q value is 0 only when reset is asserted.)
-
When will such an assertion be evaluated? I see that the assertions you have coded are evaluated at 0, 1 and 11ns. On what basis have these points of evaluation been chosen by the simulator?
-
The assertion fails at 0 and 11ns. How do we get a clean assertion at all time stamps?
-
Any particular reason why you have chosen to add an assertion on cnt (in addition to q)?
Thanks for continuously looking into this.