`timescale 1ns/1ps
module tb;
wire p;
logic q,clk;
initial begin
clk=0;
end
always #5 clk=~clk;
assign p = q;
always@(*) $display($time,"clk:",clk ," A p =%d, q=%d ", p,q);
initial begin
q <= 0; //NBA1
q <= 1; //NBA2
$display($time,"clk:",clk ," I p =%d, q=%d ", p,q);
end
initial
begin
#4;
$finish;
end
endmodule
/* Result
0clk:0 I p =x, q=x
0clk:0 A p =x, q=x
0clk:0 A p =1, q=1
*/
Why, always block is triggered only once for 2 NBA events?
In reply to DDN:
For NBA, if you are multiple NBA in NBA slot at the same slot, then the last one will take precedence to update the value. when it moves from NBA to active for updation of value.
In LRM second 4.6, 4.7 and 4.9.4 will help you get your answer.
If you see the results.
/* Result
0clk:0 I p =x, q=x // this is because of $dsiplay inside initial block
0clk:0 A p =x, q=x // why is this?
0clk:0 A p =1, q=1 // this is because of Last NBA assignement takes the precedence and creates a update event?
*/
The always block is seeing a clk X->0 transition. Note that whether the always block triggers zero, once, or twice at time 0 is a race condition—all are valid possibilities.
Also, do not use always @(*) in SystemVerilog. Use always_comb instead.